1. Field of the Invention
The present invention relates to a tracing function used for debugging a system having a CPU (Central Processing Unit) mounted thereon and, more specifically, to a semiconductor device with a chip having a tracing function mounted in the same package that has the CPU mounted thereon.
2. Description of the Background Art
Recently, CPUs have come to be widely used in information equipment such as a personal computer and electric appliances for home use. In the development of the CPU itself and in the development of systems for the information equipment and electric appliances on which the CPUs are mounted, it is important to analyze program flow executed by the CPU.
In debugging a software of a system in which the CPU is mounted, an apparatus referred to as an ICE (In Circuit Emulator) traces memory access state of the target CPU and the process of program execution, reads values of an internal register and the like, and generates trace information. A terminal such as a personal computer (hereinafter referred to as a PC) for analysis generally processes or analyzes the trace information provided by the ICE.
Particularly, when the target CPU is an ASIC (Application Specific Integrated Circuit) microcomputer, it is often the case that an interface for debugging is added to the target CPU, so as to absorb difference among specifications of various microcomputers and to enable debugging by a common ICE.
FIG. 1 is a block diagram illustrating a debugging environment for a conventional system having a CPU mounted therein. The debugging environment includes a CPU mounting system 101, an ICE 102 and an analyzing PC 103.
ICE 102 reads an internal signal of a CPU core 111 output from CPU mounting system 101 through a processor probe 104, and stores in an internal trace memory. Analyzing PC 103 receives the trace information from the trace memory inside ICE 102 through a terminal connection line 105, and presents the trace information to the user by displaying the trace information on a display screen, for example.
CPU mounting system 101 includes a target CPU chip 110, and an RAM130. Further, target CPU110 includes a CPU core 111, a debug I/F (Interface) 112 and a peripheral circuitry 113. Further, the debug I/F 112 includes an external I/F 121 and a trace control unit 122.
CPU core 111 reads data stored in RAM130 or the like by fetching and executing an instruction, performs some processing on the data, stores the result again in RAM130, and repeats such processings.
Trace control unit 122 monitors an operation of CPU core 111, and transfers data including memory access history and an internal signal of CPU core 111 to ICE102 through external I/F 121 and processor probe 104.
In the conventional debugging environment described above, target CPU chip 110 transfers memory access history and an internal signal of CPU core 111 to ICE102 through processor probe 104. Therefore, when operation frequency of target CPU chip 110 increases, it becomes difficult for ICE 102 to sample at every clock cycle the internal signals of CPU core 111 and to write to trace memory, because of stray capacitance of processor probe 104, for example.
Further, as the number of external pins of processor probe 104 is limited, it is difficult to output sufficient amount of trace information to ICE 102, resulting in a long time necessary for debugging.
Further, it is necessary to add a debugging interface in the target CPU chip 110. Therefore, the chip area increases and production yield decreases because of the addition of functional elements and wirings, resulting in higher chip cost.